Single Electron Transistor Thesis

Single Electron Transistor Thesis-40
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With the prospect of present, transistor-based microelectronics facing serious limitations due to quantum effects and heat dissipation, alternative computing paradigms---such as quantum computers, quantum-dot cellular automata and single-electronics---have emerged, promising an extension of high-level integration and computing power beyond the above limitations.

The most promising proposals are based on solid-state systems, and readout of a computational result often requires ultra-sensitive charge detectors capable of sensing the motion of single charges on fast timescales.

In the case of using single dot with 30 nm × 80 nm × 125 nm dimension, coulomb blockade effect could be reduced by applying gate voltage higher than 3V and setting drain resistance higher than source's.

Our studies show an alternative approach in modeling and simulation of electronic devices and could be potential for development of novel nanoelectronic devices.

SETS have been shown to combine all these qualities.

However, random fluctuations of the background charge in solid-state systems can affect SETs and cause errors during readout.

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We also extend our calculation by introduce some additional parameters such as; the effect of working temperature, gate voltage dependent, and the influence of resistance to the device characteristic.

We found that increasing operational temperature will promote higher current density, both in forward and reverse bias region.


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